1. Field of the Invention
This invention relates to VLSI designs, and is particularly applicable to, although not necessarily limited to, signal buffering for signals that pass up and/or down through a concurrent hierarchy.
2. Description of Background
Buffer programs in hierarchical VLSI designs select locations for placing buffers wired in series between respective driving and receiver circuits. (The terms “buffer” and “repeater” herein are interchangeable.) Typically, such a buffer program does not take into account information beyond the bounds of a particular hierarchical level it is working on. Consequently, the buffer program can produce sub-optimal buffer placement solutions for buffers that cross boundaries of the hierarchical level. Examples of sub-optimal solutions include both too many buffers and not enough buffers between a driving and receiving circuit. The case of too many buffers occurs when the combined result of buffer programs executing in different levels of hierarchy introduces too many buffers, thus impacting slack. The case of not enough buffers occurs when the combined result of buffer programs executing in different levels of hierarchy docs not introduce sufficient buffering, impacting slew and possibly slack.
Solutions to this problem conventionally involve communication in which entities pass load values, which are typically capacitative load values, from adjacent levels of hierarchy to their neighbors) in either a tops-down or bottoms-up fashion, meaning that load values are passed down or up (i.e., always one way or the other, but not both) through the design hierarchy. For example, in an up-passing arrangement, load values may be passed from a macro entity up to a unit entity and from the unit entity up to a chip entity, which may be designated as a parent entity. Up-passing of load information has been common. This is partly because macros, being more primitive than units, tend to get done earlier in the design than units, and units tend to get done earlier than the chip. Another reason that load values are commonly passed upward is that timing tools often are used for this communication and they tend to analyze timing in a bottoms-up fashion. Einstimer is an IBM tool used for delay-based timing. TLT is an IBM tool used to create timing rules, which are used as input for Einstimer, for primitive macros or even units.
Stated another way, in hierarchical chip design, a lot of tasks occur concurrently on respective entities of the chip. To work on a variety of parts, i.e., entities, of the chip in parallel, there must be some predetermined rules about timing boundaries among entities and there must be communication among entities. It sometimes happens that when all the entities come together there is insufficient communication or there are ill conceived rules, resulting in had repeater spacing across the hierarchical boundaries, i.e., repeaters either placed too close to one another or too far apart.
The use of tinting tools to communicate load values from one entity to another gives rise to another issue besides the issue of suboptimal buffer spacing that arises from one-way communication. That is, timing tools generally take a long time to execute timing runs, since they take into account much detail and they run many different tests. For a large chip design, a timing analysis run by a conventional timing tool may take several days.